Logic circuit emulation (or hardware emulation) may be used to verify logic circuit designs. In general, a logic circuit emulation of a designed logic circuit enables verification that the designed logic circuit functions correctly at higher speeds than a logic simulation in software is capable of providing. In addition, logic circuit emulations enable higher cycle level accuracy than instruction level simulations in software.
In a typical logic circuit emulation, the logic circuit is emulated in a limited amount of configurable logic emulation resources such as a field programmable gate array (FPGA). These logic emulation resources tend to be expensive, with larger logic circuits requiring more logic emulation resources.
There is an ever present desire to reduce costs associated with the development of logic circuits. Emulation of logic circuit designs for design verification during the development of logic circuits contributes to the overall cost associated with the development of logic circuits. Accordingly, methods and apparatus are needed for reducing the cost associated with the emulation of logic circuits. The present invention addresses this need among others.